R00155 (Kharagpur Section)

Chair: Dr C Mandal
Talk title




Venue Pt

Abhijit Chatterjee, Professor, School of ECE, Georgia Tech, Atlanta, GA, USA

Jan 09, 2018



KVR Seminar, N221 1

Abhijit Chatterjee is a professor in the School of Electrical and Computer Engineering
at Georgia Tech and a Fellow of the IEEE. He received his Ph.D in Electrical and Computer
Engineering from the University of Illinois at Urbana-Champaign in 1990.
Dr. Chatterjee received the NSF Research Initiation Award in 1993 and the NSF CAREER Award
in 1995. He has received seven Best Paper Awards and three Best Paper Award nominations.
His work on self-healing chips was featured as one of General Electric’s key technical
achievements in 1992 and was cited by the Wall Street Journal. In 1995, he was named a
Collaborating Partner in NASA’s New Millennium project. In 1996, he received the
Outstanding Faculty for Research Award from the Georgia Tech Packaging Research Center
and in 2000, he received the Outstanding Faculty for Technology Transfer Award,
also given by the Packaging Research Center. In 2007, his group received the
Margarida Jacome Award for work on VIZOR: Virtually Zero Margin Adaptive RF from
the Berkeley Gigascale Research Center (GSRC).

Dr. Chatterjee has authored over 425 papers in refereed journals and meetings
and has 20 patents. He is a co-founder of Ardext Technologies Inc., a mixed-signal
test solutions company and served as chairman and chief scientist from 2000-2002.
His research interests include error-resilient signal processing and control systems,
mixed-signal/RF/multi-GHz design and test and adaptive real-time systems.
He served as the chair of the VLSI Technical Interest Group at Georgia Tech from
2010-2012. He co-leads the Samsung Center of Excellence in High-Speed Design and
Test established at Georgia Tech in 2011.

Analog/mixed-signal/RF (AMS) systems for a variety of communication, signal
processing and control  experience a wide gamut of operating conditions
(perturbed process conditions, failures, signal/channel noise, workload demand).
As a consequence, they need to be tested and tuned in the field to maximize
performance, reliability and error-resilience while minimizing power consumption.
To enable off-line and dynamic adaptation, we propose to sense device operating
conditions using post-manufacture and real-time checking mechanisms that rely
on the use of built-in sensors and/or low-overhead function encoding techniques,
respectively.A key capability is that of being able to deduce multiple
performance parameters of the system-under-test using compact optimized stimulus
using learning algorithms. The sensors and function encodings assess the loss
in performance of the relevant systems due to workload uncertainties,
manufacturing process imperfections and failures induced by electro-mechanical
degradation. These are then mitigated through the use of algorithm-through-circuit
level compensation techniquesbased on pre-deployment simulation and post-deployment
self-learning. These techniques continuously trade off performance vs. power of
the individual software and hardware modules in such a way as to deliver the
end-to-end desired application level Quality of Service (QoS), while minimizing
energy/power consumption. Applications to wireless communications and nonlinear
control systems for both off-line testing-tuning and dynamic adaptation are discussed.

AMS systems, reliability testing, performance parameters, power minimisation
NXPs leadership in class D amplifier for the automotive market

Wilco de Boer, c/o Dr Santanu Kapat

March 7, 2018



KVR Seminar, N221 1

Wilco de Boer completed his B.S. from Department of Electrical Engineering and
Telematics, Utrecht, the Netherlands in 1996, and M.S. from Department of
Measurenment and Control Systems, Eindhoven University of Technology, the Netherlands
in 1998, and MBA from University of Phoenix, the Netherlands in 2007.
He holds Black Belt, Six Sigma for Industry. Since 1999, he has been with
semiconductor industry with proven track records in managing multi-disciplinary
(analog/mixed – signal IC design, hardware development, validation, test and
product engineering, and marketing) and multi-site programs/projects on schedule,
budget, and quality.

Since 1999, he has been with semiconductor industry with proven track records in managing
multi-disciplinary (analog/mixed-signal IC design, hardware development, validation, test and
product engineering, and marketing) and multi-site programs/projects on schedule, budget, and
quality. Since 2017, he has been serving as the Senior Director, Program Management in NXP
(Nijmegen, the Netherlands) heading worldwide Product Line Audio Amplifier with full
Responsibility of New Product Introduction Program (NPI). Prior to this, he was the Senior
Director, Program Management with Worldwide responsibility for portfolio management for
Secure Smartcard business of NXP Annual R&D budget of ~100M$. He is a highly motivated
director with a broad range of experience and expertise in Project Management and Engineering
Management (PMU, Smartcards, Audio amplifiers). He drives products through all NPI phases,
from Concept to Qualification and mass production with specialties in Research and
Development (R&D), Program Management, Project Management, PMO, PMP certified,
Blackbelt, ScrumMaster. He deals with all the design and development stages of IC design:
Architecture, Definition, Circuit, Layout, Block Design and post silicon validation.

He has international exposure with customers, suppliers, and project teams: Europe (Austria,
Belgium, Finland, France, Germany, Netherlands, UK,), US, China, India, Japan, and Korea.

According to the new market research report “Class D Audio Amplifier Market by Type (Mono
Channel, 2-Channel, 4-Channel, 6-Channel), Device (Handset, Television, Home Entertainment
Systems, Multimedia Sound Case, In-Car Audio), End-User Industry, and Geography – Global
Forecast to 2022”, the Class D audio amplifier market is expected to be worth USD 2.76 Billion by
2022, growing at a CAGR of 17.4% between 2016 and 2022. The Class D audio amplifier market has
a huge potential across consumer electronics and automotive applications in emerging economies such
as India and China. The major factor driving the Class D audio amplifier market across the world is
the rising demand for consumer electronic devices such as smartphones, in-car audio systems, and
smart televisions.
NXP semiconductor is considered to be a leader in automotive electronics, and this talk will primarily
highlight NXP’s leading role in the Audio Amplifier Market and focus on three key aspects, (i) NXP
and Automotive, (ii) Audio amplifiers, and (iii) Research and Development activities.

Automotive electronics, audio amplifiers, class D amplifier, mixed-signal integrated circuits
Reliability of Electronic Packages – Science or Art?

Dr Christopher Bailey, c/o Dr Anandaroop Bhattacharya

March 12, 2018



NKN (ECE) Seminar 1

Prof Christopher Bailey is Professor of
Computational Mechanics and Director of the
Computational Mechanics and Reliability
Group at the University of Greenwich, UK. He
has over 20 years professional experience in
electronic packaging (both microelectronics
and power electronics) with a particular focus
on design tools and modelling for electrical, thermal and
reliability assessments of electronic packaging. In the 2014 UK
Research Excellence Framework, over 70% of Professors
Bailey’s research outputs and impact of his work was rated in
the two highest categories of internationally excellent and world
Professor Bailey is considered internationally to be a pioneer in
the area of design tools and modelling for electronic packaging
and systems. In 2009 his work received the Times Award of
Outstanding Engineering Research Team, and his work in
knowledge transfer to industry has received numerous awards
including best knowledge transfer partnership in 2008. He has
published over 250 papers in journals and professional
conferences, and his work has received best paper prize at a
number of conferences; the most recent being Fraunhofer
Direct Digital Manufacturing Conference, Berlin, Germany,
2016. He is a regular invited keynote and short course
presenter at international conferences. Apart from being an
outstanding academic, Professor Bailey has consulted with
over 40 companies worldwide providing both technical
expertise and guidance.
Professor Bailey is also affiliated with the IEEE Components,
Packaging and Manufacturing Technology (CPMT) Society
where is a vice-president, and he is also leading on the co-
design, modelling and simulation activities for the
Heterogeneous Integration Technology roadmap which is
sponsored by a number of IEEE societies as well as other
professional societies such as AMSE and SEMI.

Advanced packaging has permitted the integration of
electronics into all manner of products and applications,
embedding electronics into every facet of our lives and
making them ubiquitous in every engineering system. We
are facing an ever-increasing demand in the speed and
amount of information we need to transmit, communicate
and process. To meet this demand and compete in the
international marketplace, we have to constantly seek
methods to achieve early adoption of new and emerging
technologies, improve quality and reliability, and reduce
cost. It is now generally recognized that the performance
and price of an electronic system are ultimately limited,
not so much by advancements in new device and chip
technology, but by our ability to package and
manufacture these individual chips into modules,
substrates, boards, sub-systems and systems.
Electronic packaging is one of the most critical topics that
a practicing engineer in the electronics industry must
know about. It is the science and technology that takes
the VLSI microchip and transforms it into an usable
system/product. The design of an electronic system
requires engineering expertise from many different
disciplines. In fact, cost, size, weight, manufacturability,
quality, reliability, and even commercial success of
electronic systems and products depend on holistic
system design that require emphasis on mechanical
design (based on the principles of mechanics and
thermal transport), manufacturing and materials
engineering, not just on electrical design.

Using modelling tools to predict reliability of electronic packages
is now widespread throughout the electronics systems community.
This presentation will discuss both the handbook methodology
(e.g. MIL-217) and the physics of failure (PoF) approach and provide
some examples where the PoF approach has been used for real world
applications. The presentation will then discuss challenges for
reliability modelling with advanced semiconductor packaging
technologies (e.g. 3D-IC, Wafer Level Packaging, etc).

IC packaging, thermal transport, packaging materials

Dr Debdeep Mukhopadhyay


Physical Attacks: Towards combined threat, protection and beyond

Dr Shivam Bhasin c/o Debdeep Mukhopadhyay

March 14, 2018



CSE Seminar 1

Dr Shivam Bhasin is a Senior Research Scientist at Temasek Labs, Nanyang Technical University
Singapore since 2015. His research interests include embedded security, trusted computing and
secure designs. He received his PhD from Telecom Paristech in 2011, Master’s from Mines
Saint-Etienne, France in 2008 and Bachelor’s from UP Tech, India in 2007. Before NTU, Shivam
held position of Research Engineer in Institut Mines-Telecom, France. He was also a visiting
researcher at UCL, Belgium (2011) and Kobe University (2013). and is an adjunct faculty in
Spring 2018 at IIT Kharagpur. He has co- authored several publications at recognized journals
and conferences. Shivam served in TPCs of several conferences, regularly reviews journal/
conference articles and presented multiple invited seminars/tutorials in prestigious venues.
Some of his research now also forms a part of ISO/IEC 17825 standard. He is also part of ESP Pvt
Ltd, a budding start up on Hardware Security, a start-up incubated at IIT Kharagpur.

Physical attacks have seen several advances since its initial introduction in 1996. Numerous
information leakage sources and fault injection techniques have been developed since then. Both
side-channel and fault attacks have grown along multiple axes, and are no longer limited to
cryptographic key recovery. New applications target reverse engineering, IP theft, user privacy etc.
New attack strategies also harvest the combination of these attacks.

This talk will touch three topics in particular, with practical examples:
(a) Practical combined side-channel and fault attacks on embedded devices
(b) Application of side-channel to reverse engineering of ciphers
(c) Design of generic countermeasures against side-channel and fault attacks

Side-channel attacks, fault attacks, hardware security, embedded systems
Developing products using GaN on Si Technology – Challenges and Opportunities

Dr Amitava Das, Ph.D., CEO Tagore Technology, Chicago, IL, USA & Kolkata, WB, India c/o Amit Patra

March 20, 2018



KVR Seminar 1

Amitava Das did his Ph.D. in EE from Purdue University in 1990. He worked in various roles
during his 25+ years in the semiconductor industry – first as a faculty of EE at IIT-B,
then developed 0.18um CMOS technology at APRDL, Motorola, worked as an RF IC/Module Design
Lead in Motorola’s wireless IC design division. Amitava moved to operations role at
Motorola productizing very high volume ICs with a global supply chain. Amitava co-founded
Tagore Technology with Manish Shah in Mar, 2011. Tagore Technology is a venture funded
fabless IC company located at Chicago, USA as well as Kolkata, India. Amitava has more than
30 papers and patents.

GaN technology has moved from research to development and production. GaN is an excellent
choice for broadband application replacing multiple narrow band LDMOS PA’s. In narrow band
applications, such as cellular infrastructure, GaN is winning designs above 3GHz space
displacing LDMOS. This is particularly relevant 5G infrastructure applications. GaN is also
a very promising in applications, such AESA radar. GaN on Si technology is emerging as a
strong contender for power electronics application in the mid voltage range (~ 100V-650V).
It is trying to displace high voltage CMOS, such as Super Junction (SJ) FET’s. While GaN
is a promising technology, Si technology has history of several decades in terms of
reliability, modeling, design/application infrastructure. This presentation will cover
opportunities and challenges of productizing GaN technology as observed by Tagore
Technology as well as other companies in this space. We will also highlight the challenges
of building an IC company in India especially in Kolkata. Opportunities of collaboration
between industry and academia will be discussed.

GaN, broadband, 3GHz, LDMOS, AESA radar
Challenges and Opportunities in Transportation Electrification

Dr Regan Zane, Prof Electrical and Computer Engg, Utah State University c/o Amit Patra

Mar 27, 2018

KVR Seminar 1

Dr. Regan Zane is a Professor of Electrical and Computer Engineering
and Founder and Director of the Center for Sustainable Electrified
Transportation (SELECT) and Power Electronics Lab at Utah State
University. He leads a wide range of research programs in power
electronics for electric vehicle drivetrains and charging
infrastructure, battery management systems, and dc and ac micro-grids
including grid integration of renewable energy sources and energy
storage. His programs maintain a strong emphasis on working with
government and industry to develop and transition technologies into
the marketplace.
Dr. Zane has co-authored over 120 peer-reviewed publications and the
textbook Digital Control of High-Frequency Switched-Mode Power
Converters. He received the NSF Career Award in 2004, the 2005 IEEE
Microwave Best Paper Prize, the 2007 and 2009 IEEE Power Electronics
Society Transactions Prize Letter Awards and the 2008 IEEE Power
Electronics Society Richard M. Bass Outstanding Young Power
Electronics Engineer Award. He received the 2006 Inventor of the Year,
2006 Provost Faculty Achievement, 2008 John and Mercedes Peebles
Innovation in Teaching, and the 2011 Holland Teaching Awards from the
University of Colorado. He received the Ph.D. degree in Electrical
Engineering from the University of Colorado Boulder in 1999. Prior to
joining USU, he was a faculty member at the University of Colorado-
Boulder, Colorado Power Electronics Center, CoPEC, 2001 to 2012, and
research engineer at GE Global Research Center, Niskayuna, NY, 1999 –

Transportation today consumes over 28% of energy use, produces more than 50% of air pollution,
and costs more than $1.5 trillion annually in the US. The transportation sector is the final
frontier for achieving the economic and environmental benefits of electrification.
Adoption of an electrified system offers the potential benefits of reducing total emissions
and cost of ownership by more than half over existing internal combustion engine vehicles.
Electrification also offers a shift away from dependence on oil to a highly flexible and
reliable electric grid, leveraging a wide range of local energy resources including sources
of renewable energy. However, the transition has many challenges, apparent in the fact that
after more than a decade on the market, all alternative fuel vehicles combined account for
less than 1% of vehicles on the road. This talk will discuss the technical challenges
limiting market adoption of electric vehicles introduce how wireless charging and electric
roads may help to overcome those challenges.

Electrification for transportation, emission reduction, electric grid, vehicle charging
Topic on 5G communications

Dr Nicola Marchetti, Prof, University of Dublin c/o Dr Debarati Sen

Date TBD

NKN Seminar GSSST 1


Dr Santanu Chattopadhyay



Dr V V Rao



Dr Chandan Chakraborty



c/o Chandan Chakraborty